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1/16 TDA7429L august 2000 n 3 stereo inputs n auxiliary mono input n input attenuation control in 0.5db step n treble middle and bass control n four speakers attenuators: - 4 independent speakers control in 1db steps for balance facility - independent mute function n subwoofer output (l+r) controlled in 1db step inputs n all functions programmable via serial bus description the TDA7429L is volume tone (bass middle and tre- ble) balance (left/right) processors for quality audio applications in tv and hi-fi systems, providing also an additional subwoofer control. the ac signal setting is obtained by resistor networks and switches combined with operational amplifiers. thanks to the used bipolar/cmos technology, low distortion, low noise and dc stepping are ob- tained. sdip42 ordering number: TDA7429L 3 band equalizer audio processor with subwoofer control figure 1. test circuit n.c. n.c. n.c. n.c. n.c. lp lp1 100nf var_l 2.2 m f hp2 basso_l var_r basso_r auxout_l auxout_r l_out r_out v s cref 100nf 10 m f 22 m f 220nf r_in3 0.47 m f r_in2 0.47 m f dig_gnd scl sda agnd 18nf 2.7k middle_lo middle_li 22nf 18nf 2.7k middle_ro middle_ri 22nf 100nf 5.6k bass_lo bass_li 100nf 100nf 5.6k bass_ro bass_ri 100nf treble_l 5.6nf d99au1029 2.2 m f treble_r 100nf monitor_r 100nf 42 1 14 2 3 4 5 6 23 24 37 19 20 21 22 41 15 16 17 18 32 31 30 29 28 27 26 25 13 12 11 8 7 40 39 mono input 0.47 m f l+r output 9 10 r_in1 0.47 m f 38 l_in1 0.47 m f 35 l_in2 0.47 m f 34 l_in3 0.47 m f 33 monitor_l 36
TDA7429L 2/16 figure 2. pin connection table 1. quick reference data symbol parameter min. typ. max. unit v s supply voltage 7 9 10.2 v v cl max. input signal handling 2 vrms thd total harmonic distortion v = 1vrms f = 1khz 0.01 0.1 % s/n signal to noise ratio v out = 1vrms (mode = off) 106 db s c channel separation f = 1khz 90 db treble control (2db step) -14 +14 db middle control (2db step) -14 +14 db bass control (2db step) -14 +14 db balance control 1db step (lch, rch) -79 0 db mute attenuation 100 db 1 3 2 4 5 6 7 8 9 auxout_r auxout_l l_in3 l_in1 l_in2 monitor_l monitor_r r_in1 r_in2 37 36 35 34 33 31 32 30 29 d99au1028 10 11 12 13 14 42 41 40 39 38 r_in3 cref v s 15 16 middle_ri treble_r treble_l scl sda dig_gnd r_out 28 27 26 24 25 23 22 17 18 19 20 21 lp1 n.c. hp2 l+r output mono input basso_l var_l var_r basso_r n.c. n.c. n.c. n.c. lp bass_lo bass_li bass_ro middle_lo bass_ri middle_li middle_ro l_out agnd
3/16 TDA7429L figure 3. block diagram. l_in1 0.47 m f supply v s agnd cref treble 18nf middle 2.7k middle_li middle_lo 22nf rm bass bass_li mute d99au1030 mute i 2 c bus decoder + latches spkr att rec att treble middle bass 18nf 22nf 2.7k 5.6nf mute spkr att mute rec att scl sda dig gnd r_out auxout_r l_out auxout_l 22 m f + lp1 hp2 100nf r_in3 0.47 m f 50k lpf 1 off lpf 2 l+r control 100nf lp middle_ri middle_ro 35 6 8 40 42 25 41 5 20 19 16 30 22 21 18 32 27 26 28 29 31 monitor_r treble_r 79db control 5.6nf treble_l 100nf 5.6k 100nf bass_lo 100nf 100nf 5.6k bass_ri bass_ro 79db control 79db control 2.2 m f basso_r var_r 30k + - + - 2.2 m f basso_l var_l 30k 79db control 15 12 11 13 14 17 23 37 24 50k 0.47 m f 50k 0.47 m f 50k 0.47 m f 50k 0.47 m f 50k 31.5db control r_in2 r_in1 31.5db control l_in2 l_in3 0.47 m f 50k rearin l+r output 34 33 38 39 910 vref off off rm rb surr rear fix 3band surr rear fix 3band fix var rb fix var the switches position matches the reset condition 36 monitor_l
TDA7429L 4/16 table 2. thermal data symbol description value unit r th j-pins thermal resistance junction-pins max. 85 c/w table 3. absolute maximum ratings symbol parameter value unit v s operating supply voltage 11 v t amb operating ambient temperature -10 to 85 c t stg storage temperature range -55 to +150 c table 4. electrical characteristics (refer to the test circuit t amb = 25c, v s = 9v, r l = 10k w ,v in = 1v rms ; r g = 600 w , all controls flat (g = 0db), l+r ctrl = +4db, mode = off; f = 1khz unless otherwise specified). symbol parameter test condition min. typ. max. unit supply v s supply voltage 7 9 10.2 v i s supply current 10 18 26 ma svr ripple rejection l ch / r ch out , mode = off 60 80 db input stage r in input resistance 35 50 65 k w v cl clipping level thd = 0.3% 2 2.5 v rms c range control range 31.5 db a vmin min. attenuation -1 0 1 db a vmax max. attenuation 31 31.5 32 db a step step resolution 0.5 1 db bass control g b control range max. boost/cut 11.5 14.0 16.0 db b step step resolution 1 2 3 db r b internal feedback resistance 32 44 56 k w middle control g m control range max. boost/cut 11.5 14.0 16.0 db m step step resolution 1 2 3 db r m internal feedback resistance 17.5 25 32.5 k w treble control g t control range max. boost/cut 13.0 14.0 15.0 db t step step resolution 1 2 3 db
5/16 TDA7429L control l+r c range control range - 11 +4 db s step step resolution 0.5 1 1.5 db speaker & aux attenuators c range control range 79 db s step step resolution -0.5 1 1.5 db e a attenuation set error a v = 0 to -20db -1.5 0 1.5 db a v = -20 to -79db -3 0 2 db v dc dc steps adjacent att. steps -3 0 3 mv a mute output mute condition +70 100 db r vea input impedance 21 30 39 k w audio outputs n o(off) output noise (off) output mute, flat bw = 20hz to 20khz 4 5 m v rms m v rms d distorsion a v = 0 ; v in = 1v rms 0.01 0.1 % s c channel separation 70 90 db v ocl clipping level d = 0.3% 2 2.5 vrms r out output resistance 20 40 70 w v out dc voltage level 3.8 v monitor outputs d distorsion a v = 0 ; v in = 1v rms 0.01 0.1 % s c channel separation 70 90 db v ocl clipping level d = 0.3% 2 2.5 vrms r out output resistance 20 50 85 w v out dc voltage level 4.5 v bus inputs v il input low voltage 1v v ih input high voltage 3 v i in input current -5 +5 ma v o output voltage sda acknowledge i o = 1.6ma 0.4 v table 4. electrical characteristics (refer to the test circuit t amb = 25c, v s = 9v, r l = 10k w ,v in = 1v rms ; r g = 600 w , all controls flat (g = 0db), l+r ctrl = +4db, mode = off; f = 1khz unless otherwise specified). symbol parameter test condition min. typ. max. unit
TDA7429L 6/16 1.0 i 2 c bus interface data transmission from microprocessor to the TDA7429L and viceversa takes place through the 2 wires i 2 c bus interface, consisting of the two lines sda and scl (pull-up resistors to positive supply voltage must be connected). 1.1 data validity as shown in fig. 3, the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. 1.2 start and stop conditions as shown in fig.4 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of the sda line while scl is high. 1.3 byte format every byte transferred on the sda line must contain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. 1.4 acknowledge the master (mp) puts a resistive high level on the sda line during the acknowledge clock pulse (see fig. 5). the peripheral (audioprocessor) that acknowledges has to pull-down (low) the sda line during this clock pulse. the audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can generate the stop information in order to abort the transfer. 1.5 transmission without acknowledge avoiding to detect the acknowledge of the audioprocessor, the m p can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking. figure 4. data validity on the i 2 c bus figure 5. timing diagram of i 2 c bus sda scl data line stable, data valid change data allowed d99au1031 scl sda start i 2 cbus stop d99au1032
7/16 TDA7429L figure 6. acknowledge on the i 2 c bus 2.0 software specification 2.1 interface protocol the interface protocol comprises: n a start condition (s) n a chip address byte, containing the TDA7429L address n a subaddress bytes n a sequence of data (n byte + achnowledge) n a stop condition (p) 3.0 examples 3.1 no incremental bus the TDA7429L receives a start condition, the correct chip address, a subaddress with the msb = 0 (no incre- mental bus), n-datas (all these datas concern the subaddress selected), a stop condition. 3.2 incremental bus the TDA7429L receives a start condition, the correct chip address, a subaddress with the msb = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas subaddress from "1xxx1010" to "1xxx1111" of data are ignored.the data 1 concern thesubaddress sent, and the data 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. scl 1 msb 23789 sda start acknowledgment from receiver d99au1033 ack = acknowledge s = start p = stop a = address b = auto increment s 1 0 0 0 0 0 a 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d95au226a b data subaddress data 1 to data n s 1 0 0 0 0 0 a 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d95au306 0d3 subaddress data xxx d2 d1 d0 s 1 0 0 0 0 0 a 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d95au307 1d3 subaddress data 1 to data n xxx d2 d1 d0
TDA7429L 8/16 table 5. function selection the first byte (subaddress) msb lsb subaddress d7 d6 d5 d4 d3 d2 d1 d0 b 1 <1> b = 1 incremental bus; active b = 0 no incremental bus; x 2 <2> x = indifferent 0,1 x x 0 0 0 0 input attenuation b x x x 0 0 0 1 control out l+r & subwoofer b x x x 0 0 1 0 not used b x x x 0 0 1 1 bass & natural base b x x x 0 1 0 0 middle & treble b x x x 0 1 0 1 speaker attenuation "l b x x x 0 1 1 1 aux attenuation "l b x x x 1 0 0 0 aux attenuation"r b x x x 1 0 0 1 input multiplexer, & aux out table 6. input attenuation selection msb lsb input attenuation d7 d6 d5 d4 d3 d2 d1 d0 0.5 db steps x0000 x 0 0 1 -0.5 x010-1 x 0 1 1 -1.5 x100-2 x 1 0 1 -2.5 x110-3 x 1 1 1 -3.5 4 db steps x000 0 x001 -4 x010 -8 x 0 1 1 -12 x 1 0 0 -16 x 1 0 1 -20 x 1 1 0 -24 x 1 1 1 -28 input attenuation = 0 ~ -31.5db d7 d6 d5 d4 d3 d2 d1 d0 l+r output switch x 0 (l+r) output pin active
9/16 TDA7429L table 7. out & (l+r) & subwoofer selection msb lsb d7 d6 d5 d4 d3 d2 d1 d0 subwoofer control x 0 0 subwoofer on x 0 1 not allowed x 1 0 subwoofer off x 1 1 not allowed out x0var x 1 fix l+r control x0000 +4 x0001 +3 x0010 +2 x0011 +1 x0100 0 x0101 -1 x0110 -2 x0111 -3 x1000 -4 x1001 -5 x1010 -6 x1011 -7 x1100 -8 x 1 1 0 1 --9 x1110 -10 x1111 -11 table 8. bass selection msb lsb bass d7 d6 d5 d4 d3 d2 d1 d0 2 db steps xxx10000 -14 xxx10001 -12 xxx10010 -10 xxx10011 -8 xxx10100 -6 xxx10101 -4 xxx10110 -2 xxx10111 0 xxx11111 0 xxx11110 2 xxx11101 4 xxx11100 6 xxx11011 8 xxx11010 10 xxx11001 12 xxx11000 14
TDA7429L 10/16 notes: 1. x = indifferent 0.1 2. spaeaker/aux attenuation = 0db to 79db table 9. speaker/aux att. r & l selection msb lsb speaker/aux att d7 d6 d5 d4 d3 d2 d1 d0 1 db steps x0000 x001-1 x010-2 x011-3 x100-4 x101-5 x110-6 x111-7 8 db steps x0000 0 x0001 -8 x0010 -16 x0011 -24 x0100 -32 x0101 -40 x0110 -48 x0111 -56 x1000 -64 x1001 -72 mute x101x x11xx
11/16 TDA7429L table 10. middle & treble selection msb lsb middle d7 d6 d5 d4 d3 d2 d1 d0 2 db steps 0000 -14 0001 -12 0010 -10 0011 -8 0100 -6 0101 -4 0110 -2 0111 0 1111 0 1110 2 1101 4 1100 6 1011 8 1010 10 1001 12 1000 14 treble 2 db steps 0000 -14 0001 -12 0010 -10 0011 -8 0100 -6 0101 -4 0110 -2 0111 0 1111 0 1110 2 1101 4 1100 6 1011 8 1010 10 1001 12 1000 14
TDA7429L 12/16 table 11. input/recout l & r selection msb lsb d7 d6 d5 d4 d3 d2 d1 d0 input multiplexer x 1 1 0 in1 x 0 0 0 in2 x 0 1 0 in3 aux out "l x 0 0 0 var 1 (3band) x 0 1 0 not allowed x 1 0 0 var 3 (rear) x 1 1 0 fix aux out "r x 0 0 0 var 1 (3band) x 0 1 0 not allowed x 1 0 0 var 3 (rear) x 1 1 0 fix table 12. power on reset bass & middle 2db treble 0db surround & out control + (l+r) control off + fix + max. attenuation speaker/aux attenuation l & r mute input attenuation + (l+r) switch max. attenuation + on natural base off input in1
13/16 TDA7429L figure 7. pin: treble-l, treble-r figure 8. pin: v out ref figure 9. pin: l-in, r-in, l-in2, r-in2, l-in3, r-in3, l-in4, r-in4 figure 10. pin: cref figure 11. pin: var-l, var-r figure 12. pin: lp1, lp 25k v s d95au309 20 m a gnd 10k v s d95au233a 20 m a gnd gnd 50k gnd v s v ref d94au200 20 m a 20k v s d95au336 20 m a 20k gnd 42k 20 m a v s 30k vref d95au227 sw gnd 10k v s d94au211 20 m a hp1 gnd
TDA7429L 14/16 figure 13. pin: scl, sda figure 14. pin: mono input figure 15. pin: l-out, r-out, monitor-l, monitor-r, ltr output, basso-l, basso-r, auxout_l, auxout_r figure 16. pin: bass-li, bass-ri, middle-li, middle-r figure 17. pin: bass-lo, bass-ro, middle- lo ,middle-ro d94au205 20 m a gnd 20 m a v s 50k vref d95au229 sw gnd v s d95au230 20 m a gnd 45k or 25k v s d95au231a 20 m a bass-ro,middle-lo,middle-ro bass-lo gnd : bass : middle (*) v s d95au232 20 m a bass-li,bass-ri,middle-li,middle-ri gnd (*) 45k : bass 25k : middle
15/16 TDA7429L sdip42 (0.600") a1 b e b1 d 22 21 42 1 la e1 a2 c e1 e e2 gage plane .015 0,38 e2 e3 e sdip42 dim. mm inch min. typ. max. min. typ. max. a 5.08 0.20 a1 0.51 0.020 a2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.38 0.46 0.56 0.0149 0.0181 0.0220 b1 0.89 1.02 1.14 0.035 0.040 0.045 c 0.23 0.25 0.38 0.0090 0.0098 0.0150 d 36.58 36.83 37.08 1.440 1.450 1.460 e 15.24 16.00 0.60 0.629 e1 12.70 13.72 14.48 0.50 0.540 0.570 e 1.778 0.070 e1 15.24 0.60 e2 18.54 0.730 e3 1.52 0.060 l 2.54 3.30 3.56 0.10 0.130 0.140 outline and mechanical data
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics a 2000 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 16/16 TDA7429L

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